Single Chip Combines Memory and Computation

Single Chip Combines Memory and Computation

A hardware advancement takes inspiration from the human brain’s neural network.
Modern computing has an efficiency problem—there is a growing lag between computation and memory. Since these processes reside on separate chips, time and energy are required for data transfer. The resulting traffic jam has only become more pronounced with the rise of AI and device miniaturization. 

To resolve this issue, researchers at the University of California San Diego have produced a single wafer that houses both computation and memory. Data travels within the chip similar to our brain’s neural network.  

“We demonstrated a new type of computing platform where memory and processing are naturally combined inside a single material. It enables an efficient spatiotemporal processing beyond conventional hardware architecture,” explained Yue Zhou, a postdoctoral researcher in the University of California, San Diego’s Department of Electrical and Computer Engineering. She is also the first author of the study, which was published in Nature Nanotechnology
 

Brain-inspired computing 


The platform that Zhou and her colleagues developed is a form of neuromorphic computing. This approach takes its cue from neuroscience, borrowing the principles of neural networks to create comparable pathways for hardware. The approach is akin to how biomimicry is inspired by nature, like deriving Velcro from burrs or diving flippers from duck feet.  

The perovskite-based nickelate substrate has electrical properties that are parallel to the brain’s neural network. Photo: David Baillot, UC San Diego Jacobs School of Engineering
The team’s work demonstrates how computer architecture can function more like neurons and synapses that interact simultaneously. The research seeks to remove siloes in conventional hardware.  

“The units for computing and memory are typically separate, with the computing function performed by the CPU and GPU on one chip while the memory component is handled by external memory such as DRAM. As a result, there is a huge amount of data movement between the two across chip connections,” Zhou explained. “We want to eliminate this back-and-forth that’s creating latency and energy overhead in today’s processing needs.” 

The solution lies in a quantum material, which is a perovskite-based nickelate. By cohousing numerous nodes on a shared platform, this network can perform both memory and computing. 
 

Help from a rare earth element  


Neodymium (NdNiO3) is a nickelate that exhibits magnetic properties, which are boosted through a process called hydrogen doping. This causes the hydrogen ions to self-organize into a formation much like a cloud, acting in a manner similar to the brain’s cerebrospinal fluid.  

When the ions are stimulated with voltage pulses, the resulting movement produces a transient response. This is where short-term memory properties emerge because each node can store details from recent signals.  

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Researcher Yue Zhou and team tested the chip’s capabilities using spoken digit recognition and epileptic seizure detection. Photo: David Baillot, UC San Diego Jacobs School of Engineering
“Previous research already found interesting electrical behavior inside this material, including resistive behavior similar to a programmable resistor as well as capacitor behavior,” Zhou noted. “We took it a step further by looking more closely at the array level behavior, which is how we found this spatiotemporal processing ability.”  

To document their findings, the team first ran a DC sweep to measure voltage and then compared it to voltage pulses using the microsecond time scale. 

“We were surprised to find totally different and opposite phenomena,” Zhou recounted. “When we did a DC sweep, we found a very small memory window. But when we moved to the microsecond scale, we saw an obvious current integration effect. We found that when you introduce the microsecond time scale, you need to consider the capacity behavior in the substrate. This is why we proposed a compact circuit model to explain this current integration behavior, which led the way to using this as a function to process information.” 
 

Successful pattern recognition 


Thanks to the coupled architecture, the researchers successfully tested two simulations for pattern recognition that both rely on spatiotemporal processing ability. The first demonstrated speech recognition by distinguishing spoken digits. 

“When you recognize someone’s voice, you first transform the sound into different frequency signals that define its characteristics. Then you process the information carried by those frequencies in order to decode and communicate,” Zhou explained. “Spoken digits are a simple and effective way to test if we can directly use the platform to process voice and distinguish between different patterns.” 

The next test was to flag epileptic seizures based on EEG (electroencephalogram) signals. Because every second counts when an individual has an episode, early detection is paramount so they can receive interventions that not only address the immediate crisis but prevent permanent injury or even death.    

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“For example, if only one location has a strong signal, you want it to alert the others through spatial communication,” Zhou noted. “Because this signal can also change over time, you also need the temporal processing ability to track and convey this information.” 

The spatiotemporal processing tests establish how the chip’s coupled architecture can improve hardware efficiency, especially on edge devices that are portable and compact.  

Wearable health sensors are prime applications because they benefit from on-device data processing as well as the privacy afforded by keeping information on a local level.  

Jennie Morton is an engineering and construction writer based in Iowa. 
A hardware advancement takes inspiration from the human brain’s neural network.